RTC clock synchronization buffer driver delay chip

Digital PLL System 16-SOIC -55 to 125

The MC100EP210S is a low skew 1:5 dual differential driver designed with LVDS clock distribution in mind. The LVDS or LVPECL input signal is differential and the signal is distributed to five identical differential LVDS outputs. The EP210S specifically guarantees low output-to-output skew. Optimized design, layout, and handling minimize skew within the device and from device to device. Two internal 50 ohm resistors are provided across the input. For LVDS input, the VTA and VTB pins should be disconnected. For LVPECL input, VTA and VTB pins should be connected to VTT (VCC-2.0 V) supply. Designers can take full advantage of the performance of the EP210S to distribute low-skew LVDS clocks on a chassis or main board. Special consideration should be given to differential inputs to prevent instability under no-signal conditions.