RTC clock synchronization buffer driver delay chip

The MC100LVEP111 is a low-skew 2:1:10 differential driver for clock distribution, accepting two clock sources into one input multiplexer. The PECL input signal can be differential or single-ended (if using the VBB output). The LVEP111 can use HSTL inputs when operating under PECL conditions. The LVEP111 is designed to guarantee low output-to-output skew. Optimized design, layout, and handling minimize skew within and between devices. To ensure the tightest skew, both sides of the differential output are equally terminated to 50Ω, even if only one side is used. If not all ten pairs are used, all output pairs are similarly terminated to the same package side, whether used or not. If no outputs are used on one side, leave these outputs open circuited (unterminated). This keeps output skew to a minimum. Failure to do so will result in a 10-20 ps skew margin loss (propagation delay) in the output being used.

The MC100EP195B is a Programmable Delay Chip (PDC) mainly used for clock de-skew and timing adjustment. It provides variable latency for differential NECL/PECL input transitions. The delay section consists of a programmable matrix of gates and multiplexers, as shown in the logic diagram in Figure 2. The EP195B delay increments are digitally selectable with a resolution of approximately 10 ps and a net range of up to 10.2 ns. The desired delay is selected by the value of 10 data select inputs D(9:0), controlled by LEN (pin 10). A low on LEN enables a transparent load mode with real-time latency values ​​determined by D(9:0). A low-high transition on LEN will latch and hold the current value for any subsequent change in D(10:0). Appropriate delay values ​​for various tap numbers associated with D0 (LSB) to D9 (MSB) are shown in Table 6 and Figure 3.