RTC clock synchronization buffer driver delay chip

The MC10E/100E111 is a low skew 1:9 dual differential driver designed with clock distribution in mind. It accepts one signal input, which can be differential or single-ended (if using the VBB output). Signals are distributed as 9 identical differential outputs. An enable input is also provided. A high forces all Q outputs low and all Qbar outputs high, disabling the device. The device was specifically designed, modeled, and produced with low skew as the primary goal. Optimized design and layout help minimize gate-to-gate skew within the device, using empirical modeling to determine process control limits and ensure consistent tpd distribution from lot to lot. A reliable guaranteed low warpage device is thus produced. To ensure compliance with the tight skew specification, both sides of the differential output are equally terminated to 50Ω, even if only one side is used. In most applications, all nine differential pairs will be used and therefore terminated. If nine pairs are not required, at least one output pair needs to be terminated on the same package side (ie, share the same VCCO) as the pair to be used in order to maintain a minimum skew. Failure to do so will result in a small degradation (in the order of 10-20 ps) of the output propagation delay used, which, while not a big deal for most designs, will mean a loss of skew margin. Only the VBB pin, the internally generated supply voltage, is provided for this device. In the case of single-ended inputs, tie the unused differential input to VBB as the switch reference voltage. VBB can also re-bias the AC-coupled input. When used, decouple VBB and VCC with 0.01 μF capacitors and limit current source or sink to 0.5 mA. VBB should be left open when not in use. The 100 Series includes temperature compensation.

CDCLVP1208 Low Jitter 2 Input Selectable 1:8 General Purpose LVPECL Buffer