RTC clock synchronization buffer driver delay chip

The NB3M8T3910G is a 3:1:10 clock fanout buffer that operates from a 2.5 V / 3.3 V core VDD and a flexible 3.3 V / 2.5 V VDDO supply (VDDO ≤ VDD). 3:1 Mux Select between crystal oscillator inputs, or select one of two differential clock inputs capable of accepting LVPECL, LVDS, HCSL, or SSTL levels. The MUX select lines SEL0 and SEL1 accept LVCMOS or LVTTL levels, selecting inputs according to Table 3. When the clock input is selected, the crystal input is disabled. The differential outputs consist of two sets of five differential outputs each configurable as LVPECL, LVDS, HCSL independently of the mode. Each differential output pair configures a pair of MODEAx/Bx select lines using LVCMOS or LVTTL levels according to Table 6. The clock input level and output state are determined according to Table 5. Single-ended LVCMOS output REFOUT Synchronously enabled by the OE_SE control line using LVCMOS/LVTTL levels according to Table 4. For clock frequencies above 250 MHz, the REFOUT line should be disabled.