RTC clock synchronization buffer driver delay chip

NECL/PECL input conversion. The delay section consists of a matrix of programmable gates and multiplexers (shown in the datasheet logic diagram). The EP195 delay increment is digitally selectable with a resolution of approximately 10 ps up to 10.2 ns. Ten data select inputs D(0:9) are latched on-chip by a high signal on the Latch Enable (LEN) control, through which the desired delay can be selected. The MC10/100EP195 is a programmable delay chip (PDC), mainly used for clock deswing and timing adjustment. It has a differential variable delay. Approximate delay values ​​corresponding to the variable number of taps associated with D0 (LSB) to D9 (MSB) are given in the datasheet. Since the EP195 is designed to use a chain of multiplexers, it has a fixed minimum delay of 2.2 ns. An additional pin D10 is provided for cascading multiple PDCs to extend the programmable range. Cascading logic allows full control over multiple PDCs. Thresholds on select input pins D0-D10 are controlled by a combination of interconnections between VEF (pin 7) and VCF (pin 8) of CMOS, ECL or TTL level signals. For CMOS input levels, keep VCF and VEF open. For ECL operation, keep VCF and VEF (pins 7 and 8) shorted. For TTL level operation, connect a 1.5 V reference to VCF and leave the VEF pin open. A 1.5 kΩ or 500 Ω resistor can be placed between VCF and VEE for a 3.3 V or 5.0 V supply respectively, allowing the VCF pin to be referenced at 1.5 V. The VBB pin is used as an internally generated power supply for this device only. For the single-ended input case, connect the unused differential input to VBB as the switch reference voltage. VBB can also re-bias AC-coupled inputs. When used, decouple VBB and VCC with 0.01 μF capacitors and limit source/sink current to 0.5 mA.