RTC clock synchronization buffer driver delay chip

CDCLVD1216 Low Jitter 2 Input Selectable 1:16 General Purpose LVDS Buffer

The NB3N3010B is a precision low-noise clock multiplier that generates an output frequency of 12.288 MHz. This can be achieved by using a Frequency Locked Loop (FLL) technique, where a 4 kHz reference input is multiplied by 3072, or an 8 kHz input is multiplied by 1536. The frequency multiplier is selected by the S0 pin. When the ENABLEn pin is set high, both LVCMOS output drivers are disabled to logic low. The NB3N3010B operates from a single 3.3 V supply and is available in a SOIC-8-pin package or a DFN8 package. Operating from 0°C to +85°C, the NB3N3010B device is the best combination of low cost, flexibility and high performance. These features make it ideal for applications such as oversampling A-D and D-A converters from low reference frequencies, such as USB start-of-frame (SOF) pulses.