RTC clock synchronization buffer driver delay chip

The NB3L8533 is a low-skew 1:4 LVPECL clock fan-out buffer specifically designed for low output skew applications. The NB3L8533 has multiplexed clock inputs that can be driven by differential or single-ended inputs and can be used to distribute lower speed clocks as well as high speed system clocks. The CLK_SEL pin selects the differential clock inputs CLK and CLKb when low (or when left open and pulled low by an internal pull-down resistor). When CLK_SEL is high, the differential PCLK and PCLKb inputs are selected. The common enable (CLK_EN) is synchronous, so the output is only enabled/disabled when it is in the low state. This avoids short clock pulses when devices are enabled/disabled, which can happen in asynchronous control. The internal flip-flops are clocked on the falling edge of the input clock, so all relevant specification limits are referenced to the negative edge of the clock input.