RTC clock synchronization buffer driver delay chip

The NB3H5150 is a high-performance multi-rate clock growth stage that can simultaneously synthesize up to four different frequencies based on a single PLL using a 25 MHz input reference. The reference frequency can be a crystal, LVCMOS/LVTTL, LVPECL, HCSL or LVDS differential signal. The REFMODE pin selects the reference source. Three Output Groups (CLK1A/CLK1B to CLK3A/CLK3B) Generate User-Selectable Frequency: 25 MHz, 33.33 MHz, 50 MHz, 100 MHz, 125 MHz, or 156.25 MHz with Ultra-Low Noise/Jitter Performance < 0.3 ps . The fourth output bank (CLK4A/CLK4B) can generate the following integer and FRAC?N frequencies in pin-strap mode: 33.33 MHz, 66.66 MHz, 100 MHz, 106.25 MHz, 125 MHz, 133.33 MHz, 155.52 MHz, 156.25 MHz or 161.1328 MHz. More programmable frequencies are available through the I2C interface with less than 1 ps jitter performance. Detailed registration instructions will be provided in a future application note. Each output block can create two single-ended in-phase LVCMOS outputs or one LVPECL output differential pair. Each of the four output blocks can be individually powered from a separate VDDO, 2.5 V/3.3 V for LVPECL, 1.8 V/2.5 V/3.3 V for LVCMOS. The serial (I2C and SMBUS) interface is programmable for a variety of functions, including the frequency and output level of each divider block, and each block can be enabled and disabled individually.