RTC clock synchronization buffer driver delay chip

The NB3V60113G, part of the OmniClock family, is a one-time programmable (OTP), low-power, PLL-based clock generator that supports any output frequency from 8 kHz to 200 MHz. The device accepts either a fundamental mode parallel resonant crystal or a single-ended (LVCMOS) reference clock as input. It generates three single-ended (LVCMOS) outputs, or one single-ended and one differential (LVDS/HCSL) output. These output signals can be modulated using the spread spectrum function of the PLL (programmable spread spectrum type, bias and rate) for applications requiring low electromagnetic interference (EMI). Using PLL bypass mode, a copy of the input clock can be obtained on any or all outputs. The device can be powered down using the power-down pin (PD#). The internal input crystal load capacitance and output drive current provided by the device can be programmed. The device also features an automatic gain control (crystal power limiting) circuit that prevents the device from overdriving an external crystal.