RTC clock synchronization buffer driver delay chip

High performance frequency synthesizer system with integrated VCO 36-WQFN -40 to 85

3.3-V PLL clock driver with 9 outputs for DRAM applications 24-TSSOP 0 to 85

The NB4N111K is a differential input clock, 1:10 HCSL fanout buffer for ultra-low propagation delay variations. NB4N111K is suitable for HCSL clock distribution for FBDIMM applications. Inputs accept differential LVPECL, CML, or LVDS levels. Single-ended LVPECL, CML, LVCMOS, or LVTTL levels are accepted with the appropriate VREFAC supply (see Figures 5, 10, 11, 12, and 13). The clock input pins incorporate internal on-chip terminations with 50 Ω resistors.