RTC clock synchronization buffer driver delay chip

The NB3V8312C is a high-performance, low-skew LVCMOS fan-out buffer that distributes 12 ultra-low-jitter clocks based on LVCMOS/LVTTL inputs up to 250 MHz. Twelve LVCMOS output pins drive 50Ω series or parallel terminated transmission lines. These outputs can also be disabled as high impedance (tri-state) via the OE input, or enabled when high. NB3V8312C provides an enable input, CLK_EN pin, which simultaneously enables the clock output, or disables it in a low state. Because this input is internally synchronized to the input clock and only changes when the input is low, there is no output glitch or runt pulse generation. Separate VDD core and VDDO output supplies allow the output buffer to operate at a supply voltage equal to VDD (VDD = VDDO) or lower. Dual-supply operation enables lower power consumption and output level compatibility compared to single-supply operation. The VDD core supply voltage can be set to 3.3 V, 2.5 V, or 1.8 V, and the VDDO output supply voltage can be set to 3.3 V, 2.5 V, or 1.8 V, but there is a constraint that VDD >/= VDDO.