Logic device/transceiver/encoder

8-Channel, 2.7V to 3.6V Buffer with 3-State Outputs 20-SO -40 to 125

GeoPort Transceiver 20-SOIC 0 to 70

8-Channel, 4.5-V to 5.5-V Buffer 20-SOIC -40 to 85 with TTL Compatible CMOS Inputs and 3-State Outputs

Octal Registered Transceiver with 3-State Outputs 24-SSOP -40 to 85

8-Channel, 2.7-V to 3.6-V Inverter with Bus-Hold, TTL Compatible CMOS Inputs and 3-State Outputs 20-TSSOP -40 to 85

The MC74C4040A has the same pin-out as the standard CMOS MC14040. The device inputs are compatible with standard CMOS outputs; pull-up resistors are included for compatibility with LSTTL outputs. The device consists of 12 master-slave flip-flops. The output of each flip-flop feeds the next flip-flop, with half the frequency at each output of the previous one. The state counter advances once on the negative going edge of the clock input. Reset is asynchronous and active high. Due to internal ripple delays, the state changes of the Q outputs do not occur simultaneously. Therefore, the decoded output signal is prone to decode spikes and may have to be gated with the HC4040A's clock for some designs.