Logic device/transceiver/encoder

B-series logic gates are built using P- and N-channel enhancement mode devices in a monolithic structure (complementary MOS). Its primary use is where low power consumption and/or high noise immunity are required.

4-Channel, 2-Input, 4.5V to 5.5V NAND Gate 14-SOIC -55 to 125 with TTL Compatible CMOS Inputs

Enhanced Product 4-Channel, 2-Input, 2V to 3.6V OR Gate 14-SOIC -55 to 125

2-Channel, 4-Input, 2V to 6V NAND Gate 14-TSSOP -40 to 85

8-bit equivalence/magnitude comparator (P=Q) with enable 20-TSSOP -40 to 85

The LVT373 and LVTH373 contain eight latches with 3-state outputs, suitable for system applications with bus structures. When the latch enable (LE) is high, the latch is transparent to the data. When LE is low, the data that meets the input timing requirements are latched. When output enable (OE#) is low, data is presented on the bus. When OE# is high, the bus output is in a high impedance state. The LVTH373 data inputs include a bus-hold feature that holds unused inputs without the need for external pull-up resistors. These octal latches are designed for low voltage (3.3V) V

The MC14549B and MC14559B successive approximation registers are 8-bit registers that provide all the digital control and storage required for a successive approximation analog-to-digital conversion system. These parts differ by only one control input. Master Reset (MR) on MC14549B is required in cascade mode when more than 8 bits are required. The feed-forward (FF) of the MC14559B is used for register shortening when an end-of-conversion (EOC) is required after less than eight cycles. Applications for the MC14549B and MC14559B include analog-to-digital conversion with serial and parallel outputs.