Logic device/transceiver/encoder

The NB7V33M is a differential divide-by-4 clock divider with asynchronous reset. The differential clock inputs include internal 50 Ω termination resistors and accept LVPECL, CML, and LVDS logic levels. The NB7V33M generates a divide-by-4 output copy of the input clock, running at speeds up to 10GHz with minimal jitter. The reset pin is active on a rising edge. When powered on, the internal flip-flops will go into a random state. Reset allows multiple NB7V33Ms in the system to synchronize. The 16mA differential CML output provides a matched internal 50Ω termination that provides an output swing of 400mV when the external receiver is terminated into 50Ω to VCC. The NB7V33M is a 4-way version of the NB7V32M (2-way) in a low-profile 3mm x 3mm 16-pin QFN encapsulation. The NB7V33M belongs to the GigaComm family of high-performance clock products.

The MC14024B is a 7-stage ripple counter with short propagation delay and high maximum clock rate. The reset input has standard noise immunity, however the clock input has increased noise immunity due to hysteresis. The output of each counter stage is buffered.

High Speed ​​CMOS Logic Presettable Synchronous BCD Decimal Up/Down Counter 16-TSSOP -55 to 125

Automotive Serial to Parallel Interface 20-TSSOP -40 to 125

The NC7SP02 is a single-channel 2-input NOR gate belonging to the Ultra Low Power (ULP) series from Fairchild TinyLogic. For applications where battery life is critical This product is designed for 0.9V to 3.6V V