Logic device/transceiver/encoder

8-Channel, 2V to 5.5V Buffer with 3-State Outputs 20-TSSOP -40 to 125

The MC10/100EP33 is an integrated divide-by-4 divider. Differential clock input. Only the VBB pin, the internally generated supply voltage, is provided for this device. For the single-ended input case, the unused differential input is tied to VBB as the switch reference voltage. VBB can also re-bias the AC-coupled input. When used, decouple VBB and VCC through a 0.01 uF capacitor and limit the current source or sink to 0.5mA. VBB should be left open when not in use. The reset pin is asynchronous and asserted on the rising edge. On power up, the internal flip-flop will reach a random state; reset to synchronize multiple EP33s in a system. The 100 series includes temperature compensation.

CMOS Presettable-N Counter 16-SO -55 to 125

High Speed ​​CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register 16-SOIC -55 to 125