Logic device/transceiver/encoder

The MC14015B dual 4-bit static shift register is constructed using MOS P-channel and N-channel enhancement mode devices in a monolithic structure. It consists of two identical independent 4-state serial-in/parallel-out registers. Each register has independent clock and reset inputs, and a single serial data input. The register state is a D-type master-slave flip-flop. During positive clock transitions, data is transferred from one stage to the next. Each register is cleared when a high level is applied on the reset line. These complementary MOS shift registers are primarily used for buffer storage and serial-to-parallel conversion where low power consumption and/or noise immunity are required.

High Speed ​​CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register 16-PDIP -55 to 125