Logic device/transceiver/encoder

The LVX273 features eight edge-triggered D-type flip-flops with separate D inputs and Q outputs. The Common Buffered Clock (CP) and Master Reset (MR#) input load and reset (clear) all trigger simultaneously. The registers are fully edge triggered. The state of each D input, one setup time, before the low-to-high clock transition is transferred to the Q output of the corresponding flip-flop. All outputs are forced low by a low voltage level on MR#, regardless of the clock or data input. The device is suitable for applications requiring only true outputs with clock and master reset common to all storage elements. The input withstand voltage is up to 7V, and it supports the interface from 5V system to 3V system.

Dual Negative Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125