Logic device/transceiver/encoder

The MC10/100EP29 is a dual master-slave flip-flop. The device provides fully differential data and clock inputs and outputs. The MC10/100EP29 is functionally identical to the MC10/100EL29. Data enters the master latch when the clock is low and is transferred to the slave latch when the clock input is transitioning. The differential input employs special circuitry to ensure device stability under open input conditions. With both differential inputs left open, the Dbar input will be pulled down to VEE and the Dbar input will be biased to VCC / 2. The output will go to the specified state, but the state is random based on how the trigger is fired. Both flip-flops provide asynchronous override "set" and "reset" inputs. Note that the set and reset inputs cannot be high at the same time. The VBB pin (internal generated power supply) is only available for this device. For the single-ended input case, connect the unused differential input to VBB as the switch reference voltage. VBB can also re-bias AC-coupled inputs. When used, decouple VBB and VCC with 0.01uF capacitors and limit current source or sink to 0.5 mA. VBB should be left open when not in use. The 100 series includes temperature compensation.

The MC10/100EP51 is a differential clocked D-type flip-flop with reset. The device is functionally identical to the EL51 and LVEL51 devices. The reset input is an asynchronous, level-triggered signal. Data enters the master portion of the flip-flop when the clock is low, then transfers to the slave portion, and thus transfers to the output on a positive transition of the clock. The EP51's differential clock input allows the device to be used as a falling-edge triggered flip-flop. The differential inputs employ clamping circuits to maintain stability under open-circuit input conditions. When left open, the CLK input will be pulled down to VEE and the CLKbar input will be biased at VCC / 2.